In future generations of semiconductor products, feature sizes F (ground rules) of below 100 nm will be used. A feature size is understood as meaning the minimum resolution which can be achieved lithographically. As part of the ongoing improvement to the lithography processes which are used, it is possible to achieve ever smaller feature sizes, but these impose ever higher demands on the entire fabrication process.
The increasing reduction in feature sizes means that it is expected that in dynamic semiconductor memories (DRAMs) there will be a switch from a planar select transistor to a vertical select transistor, which may be integrated in the upper part of the trench capacitor. This change in the arrangement of storage capacitor and select transistor is caused on the one hand by the physical limits which exist for planar transistors with channel lengths of less than 100 nm. By way of example, such short channel lengths conceal the risk of increased leakage currents. Moreover, the small cross section of the channel limits the maximum level of current which can flow. On the other hand, the change to a vertical cell design is justified by the desire to achieve memory cells which are as compact as possible, i.e. have a small lateral extent. The size of memory cells is in many cases the product of F*F. A further problem which makes a change to vertical cell designs appear desirable is the formation of the connection (buried strap) between the inner electrode of the trench capacitor and the select transistor, since this connection, on account of the outdiffusion of dopants, is of a certain size and therefore entails the risk of crosstalk between adjacent memory cells.
In the case of a vertical transistor, unlike in the case of a lateral transistor, the transistor channel runs in the vertical direction with respect to the main plane of the semiconductor substrate.
Furthermore, memory cells with a vertical transistor have the fundamental advantage that in these cells the channel length of the select transistor can be set independently of the feature size F used.
Methods for fabricating a vertical transistor in a trench are described, for example, in U.S. Pat. No. 6,093,614 and U.S. Pat. No. 5,365,097. In both methods, an epitaxial semiconductor layer is deposited on a side wall of the capacitor trench in order to form the vertically running channel region. Diffusion of dopants out of the trench which has been filled with doped polysilicon results in the formation of a drain region in the epitaxial semiconductor layer. A problem found in these methods is that the outdiffusion is not spatially limited to the epitaxial semiconductor layer, but rather continues into the single-crystal semiconductor substrate and may therefore combine with outdiffusion regions of adjacent memory cells. A further drawback of the known methods is that the epitaxial semiconductor layer also grows on the polysilicon at the trench base. On account of the polycrystalline substrate material, the epitaxial semiconductor layer at that location may likewise only be polycrystalline, and consequently the epitaxial semiconductor layer is not free of crystal lattice defects. In particular, when the semiconductor layers which have been deposited on the polycrystalline substrate material and on the single-crystal semiconductor material of the side walls grow together, an epitaxial closing joint, which is characterized by an accumulation of crystal lattice defects, is formed. However, crystal lattice defects have adverse effects on the transistor properties.